System - Chip Test Strategies

A major challenge in realizing core-based system-chips is the adoption of adequate test and diagnosis strategies. this paper focuses on the current industrial practices in test strategies for system-chips. It discusses the challenges in testing embedded cores, the testing requirements for individual cores, and their test access mechanisms. It also covers the integrated test strategies for system-chips based on reusable cores. In addition to the state-of-the-art practices in testability schemes, this paper covers the current standardization efforts for embedded core test interface mechanisms. 1: Introduction Today's embedded cores incorporated into system-chips cover a very wide range of functions, while utilizing an unprecedented range of technologies, from logic to DRAM to analog. They often come in hierarchical compositions. For instance, a complex core may embed one or more simple cores. An example system-chip design is shown in Figure (1), where a cores of various functions are demonstrated. These cores typically come in a wide range of hardware description levels. They spread from fully optimized layouts in GDSII format to widely flexible RTL codes. Embedded cores are categorized into three major types based on their hardware description level: soft, firm and hard [15]. Each type of core has different modeling and test requirements. The three types of cores offer trade-off. Soft cores leave much of the implementation to the designer, but are flexible and process-independent. Hard cores have been optimized for predictable performance, but lack flexibility. Firm cores offer a compromise between the two. The emerging process of plug-and-play with embedded cores from diverse sources faces numerous challenges in the areas of system-on-chip design, integration, and test. This paper analyzes the test and diagnosis challenges and discusses the current solutions to create testable core-based system-chips. The paper mainly covers the common practices in the industry and shed light on the ongoing efforts to contain today's challenges. In section 2, the paper discusses the testing challenges in core-based system-chips. Section 3 describes the existing strategies to address core internal test. Section 4 covers embedded core peripheral access mechanisms. Section 5 discusses the overall system-chip test and diagnosis solutions. Finally, Section 5 concludes the paper. In this section, the main test challenges in system-chips are analyzed and compared to the conventional system-on-board (SOB) ones. In addition to the major differences here, we have to note that system-chips do also share the typical testing challenges of the traditional deep-submicron chips, such as defect/fault coverage, overall …